A Type Two PLL filter system has the well known form shown below in FIG. 1. A charge pump circuit operates under the control of a phase/frequency detector to develop a voltage across the filter network formed by resistor (R1), and capacitor (C1 and C2) which provides the input to a voltage controlled oscillator (VCO). The poles of the filter are set by time constants t=R1(C1+C2) and t2=R1C2 and in many applications it is necessary to tune this filter network during operation, for example to compensate for process/operating changes or to change the dynamics of the PLL system during a different mode of operation. When this filter is integrated, this is often performed by changing one of the capacitor values, usually C1. However, C1 is also a parameter in the open loop gain of the PLL and changes in its value often necessitate a change in another of the gain parameters such as the charge pump current to prevent the PLL gain from also changing.
One method of keeping a constant gain is to maintain a fixed relationship between τ1 and τ2 and changing C2 proportionally with C1. This introduces more complexity since it is difficult for C1 to accurately track C2 because of their different bias conditions. A capacitor is relatively easy to adjust within integrated circuit application and can be conveniently formed using a MIS (metal-insulator-semiconductor) or diffused junction structure. A proportion of this capacitance can be controlled by adjusting the bias on this structure which can be done with switching transistors or through some form of continuous control using a linear circuit.
The switching devices are large so as to reduce the parasitic resistance that is introduced. This in turn introduces parasitic capacitances so the design of this arrangement can be difficult.
Furthermore it is problematic to implement capacitors within integrated circuit processes when one side of the capacitor does not connect to ground, that is a floating capacitor. When a capacitor is implemented in this ‘floating’ configuration, it will normally have a significant parasitic capacitance to ground and occupies a greater silicon area for the same value of capacitance. When implementing switching devices, these are often also more conveniently configured as switches to ground and so this tends to favour the adjustment of the component at this side of the filter normally combined with C1.
As has already been mentioned in the disclosure, adjusting C1 affects the gain of the PLL system and so normally requires a further secondary adjustment (normally to the charge pump current). Another problem is that adjusting C1 only changes the lower frequency pole τ1 and usually it would be desirable to change both poles τ1 and τ2 simultaneously to maintain a transient response. However, adjustment of the second capacitor C2 is more difficult and often not implemented.
It is desirable to allow the adjustment of both poles simultaneously which avoids the problems of adjusting a single pole only. Retaining a fixed relationship between the two poles in the filter maintains a given transient response for the PLL system.